Design of Coarse Grain Architecture with Active Reconfiguration for SoC

coarse grain reconfigurable architectures are specially suited for the systems where power consumption and flexibility is important factor while performing large computational operation. CGRA mostly used as an accelerator for various applications to get high throughputs and parallelism. This paper gives design summary of novel coarse grain architecture which can be used as an accelerator for the various applications in Wimax communication domain. The architecture consist of processing elements (PEs), configuration controller and interconnection network on a single chip.